Technical Field
The invention relates to a power conversion technique. Particularly, the invention relates to a time signal generator adapted to a power converter and a time signal generating method.
Related Art
FIG. 1 is a schematic diagram of a conventional power converter. FIG. 2 is a waveform diagram of the conventional power converter. Referring to FIG. 1 and FIG. 2, the conventional power converter 100 generally adopts a constant on time architecture. A ramp generator 140 generates a ramp signal Xramp having a constant triangular wave. A comparator 110 compares an error signal Xerr with the ramp signal Xramp to generate a comparison signal Xcm. A time control circuit 120 generates a pulse width modulation (PWM) signal Xpwm according to the comparison signal Xcm, an input voltage Vin and an output voltage Vout, where a width of an on time Ton of each period of the PWM signal Xpwm is a constant value, and the width of the on time Ton relates to the input voltage Vin and the output voltage Vout.
In the power converter 100, the comparator 110 generates the comparison signal Xcm according to the error signal Xerr and the ramp signal Xramp. The time control signal 120 determines the on time Ton for outputting the PWM signal Xpwm according to the comparison signal Xcm. An amplitude of the error signal Xerr relates to a feedback signal Vfb and a reference voltage Vref. At a moment for deciding the on time Ton for outputting the PWM signal Xpwm, the time control circuit 120 starts to calculate and generate the on time Ton, and the on time Ton of each period of the PWM signal Xpwm is constant.
Although the conventional operation architecture of pulse width modulation may achieve an effect of fixed frequency, when an equivalent series resistance ESR of a capacitor CL and an equivalent series resistance DCR of an inductor L on an output terminal of the power converter 100 are all very small, the energy compensated by the capacitor CL and the inductor L in response to a load transient variation is delayed, so that the feedback signal Vfb and the error signal Xerr are also delayed. The original error signal Xerr generated by the compensation circuit 130 cannot be used to converge the output voltage Vout. Moreover, since the on time Ton of the ramp signal Xramp is constant, a time length of the on time Ton cannot be changed along with the load transient variation. The above reasons lead to unstable oscillation of the output voltage Vout of the power converter 100.
FIG. 3 is a circuit diagram of the conventional time control circuit. Referring to FIG. 3, the time control circuit 320 includes a current source It, P-type metal oxide semiconductor (MOS) transistors MP1 and MP2, a switch S3, a capacitor C1 and a comparator 322. The current source It, the P-type MOS transistors MP1 and MP2 construct a current mirror. The current source It relates to the input voltage Vin. When the PWM signal has a logic high level, the inverted signal PWMB of the PWM signal has a logic low level, and the switch S3 is turned off. Moreover, when a current M*It obtained by multiplying the current source It by an M-multiple amplification coefficient is used to charge the capacitor C1 until a level of the charging voltage Xc is greater than the output voltage Vout, the comparator 322 ends counting the on time Ton.
FIG. 4 is a waveform diagram of a conventional counting mechanism capable of adjusting the on time. Referring to FIG. 4, the counting mechanism capable of adjusting the on time takes the error signal Xerr related to the output voltage as an upper boundary for ending the counting, especially in case of the load transient variation, variable counting is adopted. However, when the energy of the output voltage is sufficient, such counting mechanism keeps counting in order to increase the on time Ton.
FIG. 5 is a waveform diagram of a constant type counting mechanism and the counting mechanism capable of adjusting the on time of the conventional technique. Referring to FIG. 5, when the circuit structure of the power converter adopts the constant type counting mechanism, the related waveform thereof is the output voltage Vout and an inductor current IL illustrated in FIG. 5. When the circuit structure of the power converter adopts the counting mechanism capable of adjusting the on time, the related waveform thereof is the output voltage Vout1 and an inductor current IL1 illustrated in FIG. 5. Observing the waveform of the inductor current IL and the waveform of the inductor current IL1, it is known that a climbing speed of the waveform of the inductor current IL1 is faster.
As shown in FIG. 1, when an equivalent series resistance ESR of a regulation capacitor CL and an equivalent series resistance DCR of an inductor L at an output terminal are all very small, the original error signal Xerr generated by the compensation circuit 130 cannot provide enough stability to the loop, which may cause unstable oscillation of the output voltage Vout. Referring to FIG. 5 again, by observing the waveform of the inductor current IL1, it is known that a variation pattern of the current value of the inductor current IL1 is that the current value is first pulled high drastically and then pulled low drastically. The waveform of the inductor current IL1 presents several oscillations, and finally the current value is stabilized to a current value of a load current Iload. Although the counting mechanism capable of adjusting the on time can be used to ameliorate a settling time of the constant type counting mechanism, the waveform of the output voltage Vout1 is still oscillated, which is not specifically ameliorated actually.